An Ultra Low-power Current-mode Sense Amplifier for Sram Applications

A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

[1]  Luca Benini.  Leading edge low power design [SoCs] , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[2]  Y. K. Seng.  New current conveyor for high-speed low-power current sensing , 1998 .

[3]  Chong-Min Kyung,et al.  Conforming block inversion for low power memory , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[4]  G. S. Visweswaran,et al.  A low power 256 KB SRAM design , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[5]  Li Xiao-ming,et al.  A fast low power embedded cache memory design , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[6]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[7]  Kiat Seng Yeo,et al.  CMOS/BiCMOS ULSI : low voltage, low power , 2001 .

[8]  Kiat Seng Yeo,et al.  High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration , 2002 .

[9]  Kazuyuki Nakamura,et al.  High speed submicron BiCMOS memory , 1995 .

[10]  Mohamed I. Elmasry.  Low power VLSI CMOS circuit design , 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

[11]  S. Kang,et al.  Elements of low power design for integrated systems , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[12]  Dong Sam Ha,et al.  Development of a low-power SRAM compiler , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[13]  R. Irani,et al.  A bipolar load CMOS SRAM cell for embedded applications , 1995, IEEE Electron Device Letters.

[14]  Liter Siek,et al.  High-speed hybrid current-mode sense amplifier for CMOS SRAMs , 1992 .

[15]  Evert Seevinck,et al.  Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[16]  Chong-Min Kyung,et al.  Customization of a CISC processor core for low-power applications , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).