Verilog Functional Model Extraction from FPGA Design Data

XDL is a text-based language that represents XILINX FPGA design data which includes mapping, placement and routing information as well as configuration information. FPGA tool developers may utilize XDL to improve their tools performance for mapping, placement, routing, and etc. This paper presents a scheme to extract Verilog functional model from XDL produced during synthesis process. The scheme can be applied with some modifications to other applications that deal with XDL. With experiments, we show that the proposed scheme works correctly by comparing the simulation results of the original Verilog file and the extracted one for several Verilog examples.