Computation beyond moore's law: Adaptive field-effect devices for reconfigurable logic and hardware-based neural networks

The success of integrated silicon technology is based on the down-scaling of minimum feature sizes of silicon field-effect devices (MOSFETs) in a complementary circuit configuration (CMOS) according to Moore's Law. Reducing the feature size provides more components per chip and higher speed. However, this continuous miniaturization of MOSFETs will come to an end as CMOS scaling will soon approach atomic dimensions. To take computation beyond Moore's Law requires breaking at least with two major paradigms: (1) High computing performance is directly related to high switching speeds of the single device and (2), the separation of memory and computing. In this work we report on a novel adaptive nanowire field-effect transistor (a-NWFET) architecture which provides a release from paradigms (1) as well as (2). The fabricated a-NWFETs are originally ambipolar nanowire devices, using midgap Schottkybarrier contacts as source and drain (S/D) electrodes. The final unipolar a-NWFET device type (i.e. NMOS or PMOS) can be created by applying an electric bias at the back-gate. The ability to select the transistor type by the application of an electrical signal to the back-gate adds to the versatility of the device concept, where the two complementary device types are interchangeable on the fly. A simple and versatile device structure for logic and intrinsic memory applications with the potential to realize novel reconfigurable logic architectures and hardware-based neural networks will be presented.