Enhancing design robustness with reliability-aware resynthesis and logic simulation

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29--40% with only 5--13% area overhead.

[1]  Diana Marculescu,et al.  MARS-C: modeling and reduction of soft errors in combinational circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Bin Zhang,et al.  FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[3]  Nur A. Touba,et al.  Partial error masking to reduce soft error failure rate in logic circuits , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[4]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  D. Sylvester,et al.  Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[6]  Robert K. Brayton,et al.  Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[7]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[8]  Andreas G. Veneris,et al.  Seamless Integration of SER in Rewiring-Based Design Space Exploration , 2006, 2006 IEEE International Test Conference.

[9]  Naresh R. Shanbhag,et al.  Soft-Error-Rate-Analysis (SERA) Methodology , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[11]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Qi Zhu,et al.  SAT sweeping with local observability don't-cares , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Ming Zhang,et al.  A soft error rate analysis (SERA) methodology , 2004, ICCAD 2004.

[14]  Igor L. Markov,et al.  Node Mergers in the Presence of Don't Cares , 2007, 2007 Asia and South Pacific Design Automation Conference.

[15]  Kartik Mohanram,et al.  Accurate and scalable reliability analysis of logic circuits , 2007 .

[16]  David Blaauw,et al.  An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.