Proof nets and Boolean circuits

We study the relationship between proof nets for mutiplicative linear logic (with unbounded fan-in logical connectives) and Boolean circuits. We give simulations of each other in the style of the proofs-as-programs correspondence; proof nets correspond to Boolean circuits and cut-elimination corresponds to evaluation. The depth of a proof net is defined to be the maximum logical depth of cut formulas in it, and it is shown that every unbounded fan-in Boolean circuit of depth n, possibly with stC0NN/sub 2/ gates, is polynomially simulated by a proof net of depth O(n) and vice versa. Here, stC0NN/sub 2/ stands for st-connectivity gates for undirected graphs of degree 2. Let APN/sup i/ be the class of languages for which there is a polynomial size, log/sup i/-depth family of proof nets. We then have APN/sup i/ = AC/sup i/(stCONN/sub 2/).

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