Variable Length Packet Switches: Input Queued Fabrics with Finite Buffers, Speedup, and Parallelism

We investigate non blocking, variable length packet switches by focusing on performance evaluation and architectures to increase the throughput of such switches. With TCP/IP becoming the dominant protocol suite in the Internet, the analysis of variable length packet switches is necessary to understand the performance of the core routers and switches. We first present analytic models for delays and overflow probabilities in a variable length packet switch with finite buffers for both Poisson and self-similar packet arrival processes. The second part of the paper investigates various means to increase the throughput of these switches. As an alternative to VOQ-CIOQ switches that are known to be necessary to provide practical 100% throughput and QoS we consider a FIFO-CIOQ switch with speedup and multiple parallel planes of switches to minimise the delay in the input queue. We present analytic models for evaluating the impact of speedup and parallelism on increasing the throughput of the switch and show that with a parallelism of 4, it is possible to achieve 99.9% throughput.

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