Simulating Resistive-Bridging and Stuck-At Faults

The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time

[1]  Siyad C. Ma,et al.  A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  Terumine Hayashi,et al.  Faulty resistance sectioning technique for resistive bridging fault ATPG systems , 2001, Proceedings 10th Asian Test Symposium.

[3]  Michel Renovell,et al.  The concept of resistance interval: a new parametric model for realistic resistive bridging fault , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[4]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Jacob A. Abraham,et al.  A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Tracy Larrabee,et al.  Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.

[7]  Florence Azaïs,et al.  Detection of Defects Using Fault Model Oriented Test Sequences , 1999, J. Electron. Test..

[8]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[9]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[10]  Yervant Zorian,et al.  SRAM-Based FPGAs: Testing the Embedded RAM Modules , 1999, J. Electron. Test..

[11]  Michele Favalli,et al.  Bridging fault modeling and simulation for deep submicron CMOS ICs , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Bernd Becker,et al.  Automatic test pattern generation for resistive bridging faults , 2004, Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).

[13]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[14]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[15]  Tristan Derème Test en tension des courts-circuits en technologie CMOS , 1995 .

[16]  Janak H. Patel,et al.  E-PROOFS: A CMOS bridging fault simulator , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[17]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[18]  John M. Acken,et al.  Fault Model Evolution For Diagnosis: Accuracy vs Precision , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[19]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[20]  Kozo Kinoshita,et al.  Precise test generation for resistive bridging faults of CMOS combinational circuits , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[21]  Bernd Becker,et al.  Efficient bridging fault simulation of sequential circuits based on multi-valued logics , 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.

[22]  D. M. H. Walker,et al.  PROBE: a PPSFP simulator for resistive bridging faults , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[23]  D. M. H. Walker,et al.  Accurate fault modeling and fault simulation of resistive bridges , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[24]  Michel Renovell,et al.  CMOS bridging fault modeling , 1994, Proceedings of IEEE VLSI Test Symposium.

[25]  Janak H. Patel,et al.  BART: a bridging fault test generator for sequential circuits , 1997, Proceedings International Test Conference 1997.

[26]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[27]  Michele Favalli,et al.  Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).