Process cruise control: event-driven clock scaling for dynamic power management

Scalability of the core frequency is a common feature of low-power processor architectures. Many heuristics for frequency scaling were proposed in the past to find the best trade-off between energy efficiency and computational performance. With complex applications exhibiting unpredictable behavior these heuristics cannot reliably adjust the operation point of the hardware because they do not know where the energy is spent and why the performance is lost.Embedded hardware monitors in the form of event counters have proven to offer valuable information in the field of performance analysis. We will demonstrate that counter values can also reveal the power-specific characteristics of a thread.In this paper we propose an energy-aware scheduling policy for non-real-time operating systems that benefits from event counters. By exploiting the information from these counters, the scheduler determines the appropriate clock frequency for each individual thread running in a time-sharing environment. A recurrent analysis of the thread-specific energy and performance profile allows an adjustment of the frequency to the behavioral changes of the application. While the clock frequency may vary in a wide range, the application performance should only suffer slightly (e.g. with 10% performance loss compared to the execution at the highest clock speed). Because of the similarity to a car cruise control, we called our scheduling policy Process Cruise Control. This adaptive clock scaling is accomplished by the operating system without any application support.Process Cruise Control has been implemented on the Intel XScale architecture, that offers a variety of frequencies and a set of configurable event counters. Energy measurements of the target architecture under variable load show the advantage of the proposed approach.

[1]  Jack J. Dongarra,et al.  A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters , 2000, ACM/IEEE SC 2000 Conference (SC'00).

[2]  Frank Bellosa,et al.  The benefits of event: driven energy accounting in power-sensitive systems , 2000, ACM SIGOPS European Workshop.

[3]  Johannes G. Janzen.  Calculating Memory System Power for DDR SDRAM , 2001 .

[4]  Frank Bellosa,et al.  The Case for Event-Driven Energy Accounting , 2001 .

[5]  Trevor Pering,et al.  Energy Efficient Voltage Scheduling for Real-Time Operating Systems , 1998 .

[6]  Margaret Martonosi,et al.  Run-time power estimation in high performance microprocessors , 2001, ISLPED '01.

[7]  Jason Flinn,et al.  Power and Energy Characterization of the Itsy Pocket Computer (Version 1.5) , 2000 .

[8]  Miodrag Potkonjak,et al.  On-line scheduling of hard real-time tasks on variable voltage processor , 1998, ICCAD.

[9]  Mahmut T. Kandemir,et al.  Using complete machine simulation for software power estimation: the SoftWatt approach , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[10]  Jason Flinn,et al.  Quantifying the energy consumption of a pocket computer and a Java virtual machine , 2000, SIGMETRICS '00.

[11]  Lance M. Berc,et al.  Continuous profiling: where have all the cycles gone? , 1997, TOCS.

[12]  D. Brooks,et al.  Live, Runtime Power Measurements as a Foundation for Evaluating Power/Performance Tradeoffs , 2001 .

[13]  The Performance Implications of Locality Information Usage in Shared-Memory . . . , 1996 .

[14]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[15]  Frank Bellosa,et al.  Process Cruise Control: Throttling Memory Access in a Soft Real-Time Environment , 1997, SOSP 1997.

[16]  Trevor Mudge,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001 .

[17]  Kang G. Shin,et al.  Real-time dynamic voltage scaling for low-power embedded operating systems , 2001, SOSP.