Challenges in High Current On-Chip Voltage Stacked Systems

Due to the increasing throughput of high performance integrated circuits, the power consumption of recent high performance computing systems has grown significantly, leading to high on-chip current demand. The large current flowing within the power delivery network leads to challenging issues such as electromigration, low power efficiency, and thermal hotspots. As a technique to reduce on-chip current demand, voltage stacking has become a topic of growing interest within the industrial and academic communities. The challenges of on-chip voltage stacking are however significant. The limitations of relying on on-chip decoupling capacitors when load imbalances occur within a high current system are reviewed. To manage these load imbalances, a ladder topology switched capacitor converter is proposed to regulate the voltages between layers within a voltage stacked system. A 20X improvement in voltage drop is demonstrated on a case study. The current path within a voltage stacked system is quite different from a standard system. A horizontal current path is formed due to the serial connection between layers, producing large parasitic impedances within the power network. The on-chip power network within a voltage stacked system therefore requires careful consideration and specialized design techniques.