Reduction operations on a distributed memory machine with a reconfigurable interconnection network

We are interested in performing reduction operations with distributed memory machines whose interconnection networks are reconfigurable. More precisely, we focus on machines whose interconnection graph can be configured as any graph of maximum degree d. We discuss the best way of interconnecting the p processors as a function of p, d, and some problemand machine dependent-parameters that characterize the ratio communication/arithmetic for the reduction operation. Experiments on Transputer-based networks are in good accordance with the theoretical results.