Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450/spl deg/C. Compared to pure SiO/sub 2/, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g/sub m/) of 1000 mS/mm is obtained for L/sub gate/=70 nm and t/sub OX/=1.5 nm. Peak cutoff frequency (f/sub T/) of 120 GHz and a low minimum noise figure (NF/sub min/) of 0.5 dB with associated gain of 19 dB are obtained for t/sub OX/=2 nm and L/sub gate/=80 nm.

[1]  E. Morifuji,et al.  High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs , 1996, International Electron Devices Meeting. Technical Digest.

[2]  Tadahiro Ohmi,et al.  Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing , 1997 .

[3]  T. P. Ma,et al.  Ultra-thin Nitride/oxide Stack Dielectric Produced By In-situ Jet Vapor Deposition , 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

[4]  E. Morifuji,et al.  0.2 /spl mu/m analog CMOS with very low noise figure at 2 GHz operation , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[5]  Y. Taur,et al.  A new 'shift and ratio' method for MOSFET channel-length extraction , 1992, IEEE Electron Device Letters.

[6]  I. Chen,et al.  A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V) , 1996, International Electron Devices Meeting. Technical Digest.

[7]  G.A. Brown,et al.  Ultrathin nitrogen-profile engineered gate dielectric films , 1996, International Electron Devices Meeting. Technical Digest.

[8]  Byung-Gook Park,et al.  A novel 0.1 μm MOSFET structure with inverted sidewall and recessed channel , 1996, IEEE Electron Device Letters.

[9]  Sugii,et al.  Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs , 1997, 1997 Symposium on VLSI Technology.

[10]  Rogers,et al.  Fabrication Of 0.06 /spl mu/m Poly-si Gate Using Duv Lithography With A Designed Si/sub x/O/sub y/N/sub z/ Film As An Arc And Hardmask , 1997, 1997 Symposium on VLSI Technology.

[11]  T. Ohguro 0.2μm analog CMOS with very low noise figure at 2GHz operation , 1996 .

[12]  Toru Toyabe,et al.  Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate , 1995 .