A revised low power test architecture

Circuit switching activity during scan test is high and results in high average and instantaneous power consumption, which is becoming a concern for scan-based architecture. This paper presents a novel low power compression architecture for scan testing. A low power feedback MUX is added to the scan chains structure. Also, this paper maps the sequential test planning problems to a combinational circuit which can deal with arbitrary at-speed delay-test clock schemes.

[1]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[2]  Hans-Joachim Wunderlich,et al.  Low-power test planning for arbitrary at-speed delay-test clock schemes , 2010, 2010 28th VLSI Test Symposium (VTS).

[3]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.

[4]  Dong Xiang,et al.  Low-capture-power at-speed testing using partial launch-on-capture test scheme , 2010, 2010 28th VLSI Test Symposium (VTS).

[5]  Sandeep Bhatia.  Low power compression architecture , 2010, 2010 28th VLSI Test Symposium (VTS).

[6]  A. Arulmurugan,et al.  Survey of low power testing of VLSI circuits , 2012, 2012 International Conference on Computer Communication and Informatics.

[7]  Janusz Rajski,et al.  Low Power Embedded Deterministic Test , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[8]  Mango Chia-Tso Chao,et al.  Theoretical analysis for low-power test decompression using test-slice duplication , 2010, 2010 28th VLSI Test Symposium (VTS).

[9]  Janak H. Patel,et al.  A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Adit D. Singh,et al.  An output compression scheme for handling X-states from over-clocked delay tests , 2010, 2010 28th VLSI Test Symposium (VTS).

[11]  Yervant Zorian,et al.  On IEEE P1500's Standard for Embedded Core Test , 2002, J. Electron. Test..

[12]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[13]  Tomokazu Yoneda,et al.  Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing , 2010, 2010 28th VLSI Test Symposium (VTS).

[14]  Srivaths Ravi,et al.  A generic low power scan chain wrapper for designs using scan compression , 2010, 2010 28th VLSI Test Symposium (VTS).

[15]  Sudhakar M. Reddy,et al.  Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating , 2011, 2011 Asian Test Symposium.

[16]  Erik Jan Marinissen,et al.  The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs , 2002, J. Electron. Test..