Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation

In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.

[1]  Xingbi Chen,et al.  A High-Speed Deep-Trench MOSFET With a Self-Biased Split Gate , 2010, IEEE Transactions on Electron Devices.

[3]  M.J. Kumar,et al.  Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.

[4]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[5]  A. DasGupta,et al.  Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation , 2004, IEEE Transactions on Electron Devices.

[6]  A. Orouji,et al.  Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions , 2005, IEEE Transactions on Electron Devices.

[7]  Ken K. Chin,et al.  Dual-material gate (DMG) field effect transistor , 1999 .

[8]  A. A. Bright,et al.  A metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length , 1990 .

[9]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[10]  J. Woo,et al.  A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance , 2005, IEEE Electron Device Letters.

[11]  T. Sakamoto,et al.  Transistor operation of 30-nm gate-length EJ-MOSFETs , 1998, IEEE Electron Device Letters.

[12]  T. Tsuchiya,et al.  Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique , 1995 .

[13]  Mansun Chan,et al.  Design of sub-50 nm ultrathin-body (UTB) SOI MOSFETs with raised S/D , 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).

[14]  J.J. Liou,et al.  A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.

[15]  Hon-Sum Philip Wong.  Experimental verification of the mechanism of hot-carrier-induced photon emission in n-MOSFET's with a CCD gate structure , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[16]  S. Pidin,et al.  Short-channel single-gate SOI MOSFET model , 2003 .

[17]  Jong-Ho Lee,et al.  50 nm MOSFET with electrically induced source/drain (S/D) extensions , 2001 .

[18]  K. K. Young.  Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[19]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[20]  F. Schwierz,et al.  An Analytical Model for the Threshold Voltage Shift Caused by Two-Dimensional Quantum Confinement in Undoped Multiple-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.

[21]  F. Murai,et al.  Threshold voltage controlled 0.1-/spl mu/m MOSFET utilizing inversion layer as extreme shallow source/drain , 1993, Proceedings of IEEE International Electron Devices Meeting.

[22]  S. Sawada,et al.  High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions , 1992, 1992 International Technical Digest on Electron Devices Meeting.