Chortle-crf: fast technology mapping for lookup table-based FPGAs

A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented. The major innovation is a method for choosing gate-level decompositions based on bin packing. This approach is up to 28 times faster than a previous exhaustive approach. The algorithm also exploits reconvergent paths and replication of logic at fanout nodes to reduce the number of lookup tables in the circuit. The new algorithm is implemented in the Chortle-crf program. In an experimental comparison Chortle-crf requires 14 YO fewer lookup tables than Chortle [Fran90] and 10 ~o fewer lookup tables than mis-pga [Murg90a] to implement a set of benchmark networks. Chortle-crf can also implement a network as a circuit of Xilinx 3000 series Configurable Logic Blocks (CLBS). To implement the benchmark networks as circuits of CLBS Chortle-crf requires 12 70 fewer CLBS than mis-pga and 22 % fewer CLBS than XNFOPT [Xili89]. In these experiments Chortle-crf waa an average of 68 times faster than mis-pga and 30 times faster than XNFOPT. 1

[1]  Robert K. Brayton,et al.  Logic synthesis for programmable gate arrays , 1991, DAC '90.

[2]  K. Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Jonathan Rose,et al.  Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency , 1990 .

[4]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[5]  A. Gibbons.  Algorithmic Graph Theory , 1985 .

[6]  F. Brglez,et al.  McMAP: a fast technology mapping procedure for multi-level logic synthesis , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[7]  D. Gregory,et al.  SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic , 1986, 23rd ACM/IEEE Design Automation Conference.

[8]  A. El Gamal,et al.  An FPGA family optimized for high densities and reduced routing delay , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[9]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[10]  Martine D. F. Schlag,et al.  Routability-driven technology mapping for lookup table-based FPGAs , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[11]  Jonathan Rose,et al.  Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.

[12]  R. H. Freeman,et al.  A 9000-gate user-programmable gate array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.