Variability-aware low-power techniques for nanoscale mixed-signal circuits

New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored.

[1]  K. Choi,et al.  Parasitic-aware design and optimisation of RF power amplifiers , 2002 .

[2]  Kiyong Choi,et al.  Parasitic-aware design and optimization of a CMOS RF power amplifier , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Florence Azaïs,et al.  A methodology and design for effective testing of voltage-controlled oscillators (VCOs) , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[4]  Kyusun Choi,et al.  CMOS flash analog-to-digital converter for high speed and low voltage applications , 2003, GLSVLSI '03.

[5]  Borivoje Nikolic,et al.  Level conversion for dual-supply systems , 2004 .

[6]  Dennis Sylvester,et al.  A new algorithm for improved VDD assignment in low power dual VDD systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[7]  Niraj K. Jha,et al.  Leakage power analysis and reduction during behavioral synthesis , 2002, Proceedings 2000 International Conference on Computer Design.

[8]  Kaushik Roy,et al.  Self–precharging flip–flop (SPFF): A new level converting flip–flop , 2002 .

[9]  K. Onishi,et al.  Fabrication of high quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs using deuterium anneal , 2002, Digest. International Electron Devices Meeting,.

[10]  Kiyong Choi,et al.  Post-optimization design centering for RF integrated circuits , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[11]  James D. Meindl,et al.  Impact of within-die parameter fluctuations on future maximum clock frequency distributions , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[12]  Soo-Won Kim,et al.  A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application , 2000 .

[13]  James Kao,et al.  Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.

[14]  Dennis Sylvester,et al.  Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Kyusun Choi,et al.  Design method and automation of comparator generation for flash A/D converter , 2002, Proceedings International Symposium on Quality Electronic Design.

[16]  Azadeh Davoodi,et al.  Simultaneous V/sub t/ selection and assignment for leakage optimization , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  K. Tanaka,et al.  Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[18]  S. Mohanty,et al.  A 45 nm Flash Analog to Digital Converter for Low Voltage High Speed System-on-Chips , 2007 .

[19]  Kaushik Roy,et al.  Gate leakage reduction for scaled devices using transistor stacking , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[20]  David Blaauw,et al.  Gate oxide leakage current analysis and reduction for VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Saraju P. Mohanty,et al.  Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO , 2009, Microelectron. J..

[22]  Yu Cao,et al.  Optimizing finfet technology for high-speed and low-power design , 2007, GLSVLSI '07.

[23]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[24]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[25]  Bin-Da Liu,et al.  A new level converter for low-power applications , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[26]  Mohab Anis,et al.  Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  R. Wunderlich,et al.  Design of a Ring-Oscillator with a Wide Tuning Range in 0 . 13 μ m CMOS for the use in Global Navigation Satellite Systems , 2004 .

[28]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[29]  Michael P. Flynn,et al.  A "digital" 6-bit ADC in 0.25-μm CMOS , 2002 .

[30]  Andreas G. Andreou,et al.  Mismatch in photodiode and phototransistor arrays , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[31]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[32]  Satoshi Shigematsu,et al.  A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application , 1996, IEEE J. Solid State Circuits.

[33]  Angel Nikolaev Popov,et al.  Investigation of a Parallel Resistorless ADC , 2005 .

[34]  Jean-Olivier Plouchart,et al.  CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement , 2006, IEEE Custom Integrated Circuits Conference 2006.

[35]  P. Agnello,et al.  CMOS active pixel image sensors fabricated using a 1.8 V, 0.25 /spl mu/m CMOS technology , 1996, International Electron Devices Meeting. Technical Digest.

[36]  Kaushik Roy,et al.  Low-power design using multiple channel lengths and oxide thicknesses , 2004, IEEE Design & Test of Computers.

[37]  Saraju P. Mohanty,et al.  A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems , 2009, 2009 10th International Symposium on Quality Electronic Design.

[38]  Ranga Vemuri,et al.  Variation Aware Spline Center and Range Modeling for Analog Circuit Performance , 2008, ISQED 2008.

[39]  Chao Shen,et al.  Low voltage CMOS active pixel sensor design methodology with device scaling considerations , 2001, Proceedings 2001 IEEE Hong Kong Electron Devices Meeting (Cat. No.01TH8553).

[40]  F. Farbiz,et al.  Using Level Restoring Method for Dual Supply Voltage , 2006, 2006 7th International Symposium on Antennas, Propagation & EM Theory.

[41]  Massoud Pedram,et al.  Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[42]  Ranga Vemuri,et al.  Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[43]  Mark C. Johnson,et al.  Datapath scheduling with multiple supply voltages and level converters , 1997, TODE.

[44]  Dennis Sylvester,et al.  Fast and energy-efficient asynchronous level converters for multi-VDD design [CMOS ICs] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[45]  Orly Yadid-Pecht,et al.  Adaptive multiple resolution CMOS active pixel sensor , 2004 .

[46]  Yu Cao,et al.  Compact modeling of carbon nanotube transistor for early stage process-design exploration , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[47]  Bin-Da Liu,et al.  A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[48]  Kiyong Choi,et al.  Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier , 2003, ASP-DAC '03.

[49]  Roland E. Best.  Phase-Locked Loops , 1984 .

[50]  Mohab Anis,et al.  Dual-Vt design of FPGAs for subthreshold leakage tolerance , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[51]  David J. Allstot,et al.  NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO , 2004 .

[52]  F. Kuttner,et al.  A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[53]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[54]  D. J. Allstot,et al.  A fully integrated 0.5-5.5 GHz CMOS distributed amplifier , 2000 .

[55]  Jan Van der Spiegel,et al.  An extended frequency range CMOS voltage-controlled oscillator , 2002, 9th International Conference on Electronics, Circuits and Systems.

[56]  Massoud Pedram,et al.  Energy Minimization Using Multiple Supply Voltages , 1997 .

[57]  Nam-Seog Kim,et al.  New dynamic logic-level converters for high performance application , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[58]  Jason Cong,et al.  Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics , 2004, FPGA '04.

[59]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[60]  Jan Van der Spiegel,et al.  Linear Current-Mode Active Pixel Sensor , 2007, IEEE Journal of Solid-State Circuits.

[61]  H.C. Luong,et al.  Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback , 2005, IEEE Journal of Solid-State Circuits.

[62]  Rob A. Rutenbar,et al.  ASF: a practical simulation-based methodology for the synthesis of custom analog circuits , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[63]  Jing-Hong Conan Zhan,et al.  A comparative study of MOS VCOs for low voltage high performance operation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[64]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[65]  S. Andersson,et al.  On the power consumption of analog to digital converters , 2006, 2006 NORCHIP.

[66]  H. Sanchez,et al.  A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[67]  Kyusun Choi,et al.  Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter , 2003 .

[68]  Dirk Timmermann,et al.  Design of mixed gates for leakage reduction , 2007, GLSVLSI '07.

[69]  G. Geelen.  A 6 b 1.1 GSample/s CMOS A/D converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[70]  Dennis Sylvester,et al.  Tradeoffs between gate oxide leakage and delay for dual T/sub ox/ circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..

[71]  Kurt Keutzer,et al.  Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[72]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[73]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[74]  Kiyong Choi,et al.  Parasitic-Aware Optimization of CMOS RF Circuits , 2003 .

[75]  Kyusun Choi,et al.  A 1-GSPS CMOS flash A/D converter for system-on-chip applications , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[76]  Saraju P. Mohanty,et al.  Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[77]  Chris Clifton,et al.  A CMOS low-power ADC for DVB-T and DVB-H systems , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[78]  Robert J. Weber,et al.  A 2.4GHz low-power low-phase-noise CMOS LC VCO , 2004, IEEE Computer Society Annual Symposium on VLSI.

[79]  Eric R. Fossum,et al.  A 1.5-V 550-/spl mu/W 176/spl times/144 autonomous CMOS active pixel image sensor , 2003 .

[80]  J. Choudhury,et al.  Efficient encoding scheme for ultra-fast flash ADC , 2004, Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004..

[81]  Abbas El Gamal,et al.  Comparative analysis of SNR for image sensors with enhanced dynamic range , 1999, Electronic Imaging.

[82]  Srinivas Katkoori,et al.  Knapbind: an area-efficient binding algorithm for low-leakage datapaths , 2003, Proceedings 21st International Conference on Computer Design.

[83]  Rajendran Panda,et al.  Characterization of Standard Cells for Intra-Cell Mismatch Variations , 2008, ISQED 2008.

[84]  Michael Orshansky,et al.  Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[85]  Rajendran Panda,et al.  Statistical delay computation considering spatial correlations , 2003, ASP-DAC '03.

[86]  Saraju P. Mohanty,et al.  Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments , 2009, 2009 10th International Symposium on Quality Electronic Design.

[87]  R. Gupta,et al.  Parasitic-aware design and optimization of CMOS RF integrated circuits , 1998, 1998 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.98CH36182).

[88]  Srinivas Katkoori,et al.  Resource allocation and binding approach for low leakage power , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[89]  A. Gamal,et al.  Analysis of active pixel sensor readout circuit , 2003 .

[90]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.