A CMOS sub-harmonic mixer for direct conversion receiver

A sub-harmonic passive mixer for WiBro (2.3∼2.4GHz) in 0.18 µm COMS process has been designed. The circuit includes a differential phase splitter for the LO circuit. This architecture have a low flicker noise (20.29Hz) and a good double sideband noise figure (9.29dB) while demanding little power consumption. The input referred 1-dB compression point is −4.3dBm, IIP2 is 33.12dBm and IIP3 is −3.44dBm. In this paper, it is to understand the mechanism of SHM.

[1]  L.E. Larson,et al.  A 24-GHz CMOS Direct-Conversion Sub-Harmonic Downconverter , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[2]  M. Steyaert,et al.  A wideband IMRR improving quadrature mixer/LO generator , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[3]  A. Molnar,et al.  RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[4]  A. Abidi.  Direct-conversion radio transceivers for digital communications , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[5]  J. Laskar,et al.  Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers , 2006, IEEE Transactions on Microwave Theory and Techniques.

[6]  M. Hossain,et al.  Performance of a low voltage highly linear 24 GHz down conversion mixer in 0.18-/spl mu/m CMOS , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.