Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
暂无分享,去创建一个
[1] Giovanni De Micheli,et al. Polynomial methods for allocating complex components , 1999, DATE '99.
[2] Randal E. Bryant,et al. Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW , 2001, DAC '01.
[3] Richard Gerber,et al. Verifying systems with integer constraints and Boolean predicates: a composite approach , 1998, ISSTA '98.
[4] Sérgio Vale Aguiar Campos,et al. Symbolic Model Checking , 1993, CAV.
[5] Masahiro Fujita,et al. Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1993, 30th ACM/IEEE Design Automation Conference.
[6] Rolf Drechsler,et al. RTL-datapath verification using integer linear programming , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[7] Mahesh A. Iyer,et al. Race a word-level atpg-based constraints solver system for smart random simulation , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[8] David L. Dill,et al. CVC: A Cooperating Validity Checker , 2002, CAV.
[9] Tiziano Villa,et al. VIS: A System for Verification and Synthesis , 1996, CAV.
[10] Hans Eveking,et al. Formal Verification of Designs with Complex Control by Symbolic Simulation , 1999, CHARME.
[11] F. W. Kellaway,et al. Advanced Engineering Mathematics , 1969, The Mathematical Gazette.
[12] Franz Winkler,et al. Polynomial Algorithms in Computer Algebra , 1996, Texts and Monographs in Symbolic Computation.
[13] Sandra Fillebrown,et al. The MathWorks' MATLAB , 1996 .
[14] Zhihong Zeng,et al. LPSAT: a unified approach to RTL satisfiability , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[15] R. Bryant,et al. Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .
[16] Kurt Keutzer,et al. Functional vector generation for HDL models using linear programming and 3-satisfiability , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[17] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[18] Zhihong Zeng,et al. Taylor expansion diagrams: a new representation for RTL verification , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.
[19] A. Sangiovanni-Vincentelli,et al. Partitioned ROBDDs—a compact, canonical and efficiently manipulable representation for Boolean functions , 1996, ICCAD 1996.
[20] Emmanuel Boutillon,et al. Variable ordering for taylor expansion diagrams , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).
[21] Rolf Drechsler,et al. Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.
[22] G. de Micheli,et al. Polynomial methods for component matching and verification , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[23] Giovanni De Micheli,et al. Application of symbolic computer algebra in high-level data-flow synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Herbert B. Enderton,et al. A mathematical introduction to logic , 1972 .
[25] Zheng Zhou,et al. Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions , 1995, 32nd Design Automation Conference.
[26] Kwang-Ting Cheng,et al. Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Shobha Vasudevan,et al. Automatic Verification of Arithmetic Circuits in RTL using Term Rewriting Systems , 2003 .
[28] Mandalagiri S. Chandrasekhar,et al. Application of Term Rewriting Techniques to Hardware Design Verification , 1987, 24th ACM/IEEE Design Automation Conference.
[29] Erwin Kreyszig,et al. Advanced Engineering Mathematics, Maple Computer Guide , 2000 .
[30] E. Allen Emerson,et al. Temporal and Modal Logic , 1991, Handbook of Theoretical Computer Science, Volume B: Formal Models and Sematics.
[31] Sarma B. K. Vrudhula,et al. FGILP: an integer linear program solver based on function graphs , 1993, ICCAD '93.
[32] Zhihong Zeng,et al. Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[33] Sanjit A. Seshia,et al. Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions , 2002, CAV.
[34] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[35] Randal E. Bryant,et al. Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic , 1999, TOCL.
[36] Prashant Jain. Parameterized motion estimation architecture for dynamically varying power and compression requirements , 2002 .
[37] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[38] Kurt Keutzer,et al. Design verification and reachability analysis using algebraic manipulation , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[39] Rolf Drechsler,et al. Algorithms for Taylor expansion diagrams [IC design/verification applications] , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.
[40] Randal E. Bryant,et al. Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.
[41] Rolf Drechsler,et al. The K*BMD: A Verification Data Structure , 1997, IEEE Des. Test Comput..
[42] Rolf Drechsler,et al. Algorithms for Taylor Expansion Diagrams. , 2004 .
[43] Jacob A. Abraham,et al. Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems , 2007, IEEE Transactions on Computers.
[44] Sharad Malik,et al. Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[45] David L. Dill,et al. Automatic verification of Pipelined Microprocessor Control , 1994, CAV.
[46] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[47] Enrico Macii,et al. Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[48] M. Davio,et al. TAYLOR EXPANSIONS OF BOOLEAN FUNCTIONS AND OF'THEIR DERIVATIVES , 1972 .
[49] Randal E. Bryant,et al. *PHDD: an efficient graph representation for floating point circuit verification , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[50] Robert E. Shostak,et al. Deciding Combinations of Theories , 1982, JACM.
[51] Olivier Coudert,et al. A unified framework for the formal verification of sequential circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[52] Eugene Goldberg,et al. BerkMin: A Fast and Robust Sat-Solver , 2002, Discret. Appl. Math..
[53] Randal E. Bryant,et al. Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors , 2003, J. Symb. Comput..
[54] Rolf Drechsler,et al. Formal verification of word-level specifications , 1999, DATE '99.
[55] Wolfgang Rosenstiel,et al. Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.
[56] Dhiraj K. Pradhan,et al. Mathematical framework for representing discrete functions as word-level polynomials , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.
[57] Priyank Kalla,et al. An infrastructure for rtl validation and verification , 2002 .
[58] André Thayse,et al. Boolean Differential Calculus and its Application to Switching Theory , 1973, IEEE Transactions on Computers.
[59] Emmanuel Boutillon,et al. Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams , 2006, Proceedings of the Design Automation & Test in Europe Conference.