1-1-1 MASH ∆ Σ Time-to-Digital Converters with 6 ps Resolution and Third-Order Noise-Shaping

Two 1-1-1 MASH ∆Σ Time-to-Digital converters (TDCs) are presented in this paper. Third-order time domain noise-shaping has been adopted by the TDCs to achieve better than 6 ps resolution. Following a detailed analysis of the noise generation and propagation in the MASH ∆Σ structure, the first prototyping TDC has been realized in 0.13 μm CMOS technology. It achieves an ENOB of 11 bits and consumes 1.7 mW from a 1.2 V supply. In the second MASH TDC, a delay-line assisted calibration technique is introduced to mitigate the phase skew caused by the large comparator delay, which is the main limiting factor of the MASH TDC’s resolution. The demonstrated TDC achieves an ENOB of 13 bits and a wide input range of 100 ns. This TDC shows a temperature coefficient of 176 ppm◦C within a temperature range of -20 to 120 ◦C. It consumes only 0.7 mW and occupies 0.08 mm area (core).

[1]  Amr Elshazly,et al.  A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth , 2010, IEEE Custom Integrated Circuits Conference 2010.

[2]  Fa Foster Dai,et al.  A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology , 2009, 2009 Symposium on VLSI Circuits.

[3]  Timo Rahkonen,et al.  A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method , 2009, IEEE Journal of Solid-State Circuits.

[4]  A. Inoue,et al.  Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement , 2008, 2008 IEEE Symposium on VLSI Circuits.

[5]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[6]  R. Dutton,et al.  Minimum achievable phase noise of RC oscillators , 2005, IEEE Journal of Solid-State Circuits.

[7]  Stephan Henzler,et al.  90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[9]  Hong-June Park,et al.  A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[10]  A. Abidi,et al.  Noise in relaxation oscillators , 1983 .

[11]  S. Gierkink,et al.  A coupled sawtooth oscillator combining low jitter and high control linearity , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[12]  J. Kostamovaara,et al.  A CMOS time-to-digital converter with better than 10 ps single-shot precision , 2006, IEEE Journal of Solid-State Circuits.

[13]  Mel Bazes,et al.  Two novel fully complementary self-biased CMOS differential amplifiers , 1991 .

[14]  K. Leung,et al.  A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device , 2002, IEEE J. Solid State Circuits.

[15]  Ying Cao,et al.  A 0.7mW 13b temperature-stable MASH ΔΣ TDC with delay-line assisted calibration , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[16]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[17]  M. P. Flynn,et al.  A 1.2- mu m CMOS current-controlled oscillator , 1992 .

[18]  R. Staszewski,et al.  3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS , 2006 .

[19]  Kofi A. A. Makinwa,et al.  A CMOS Temperature-to-Digital Converter with an Inaccuracy of ± 0.5° C (3/spl sigma)from -55 to 125°C , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[20]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[21]  Paul Leroux,et al.  A 1.7mW 11b 1–1–1 MASH ΔΣ time-to-digital converter , 2011, 2011 IEEE International Solid-State Circuits Conference.