A Current-Mode Multiple-Resolution Edge-Filtering Complementary Metal Oxide Semiconductor Image Sensor Employing Self-Similitude Processing in Non-Subtraction Configuration

A non-subtraction configuration of the self-similitude image processing architecture has been developed for pixel-parallel multiple-resolution directional edge filtering. In contrast to the subtraction-separated configuration employed in our previous work, the subtraction operation has been entirely eliminated from the computation repertory of processing elements in the present configuration. As a result, the hardware organization of the multiple-resolution edge-filtering complementary metal oxide semiconductor (CMOS) image sensor has been greatly simplified, and a fully pixel-parallel self-similitude processing has been established without any complexity in interconnects. In addition, it has provided an opportunity to further apply the self-similitude architecture to other filtering operation like Gaussian filtering and Laplacian filtering. An analog edge-filtering chip implemented using current-mode computation capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.18-µm five-metal CMOS technology. The concept has been verified by chip measurements, which show that the four-directional edge filtering at multiple resolutions is accomplished at 910 frames/s for 56×56-input images.

[1]  Jacques-Olivier Klein,et al.  A DSP‐like analogue processing unit for smart image sensors , 2002, Int. J. Circuit Theory Appl..

[2]  Tadashi Shibata,et al.  Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects , 2005 .

[3]  C. Laurgeau,et al.  Fade: a vehicle detection and tracking system featuring monocular color vision and radar data fusion , 2002, Intelligent Vehicle Symposium, 2002. IEEE.

[4]  A. M. Chiang,et al.  A CCD programmable image processor and its neural network applications , 1991 .

[5]  Antoine Dupret,et al.  A programmable vision chip for CNN based algorithms , 2000, Proceedings of the 2000 6th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2000) (Cat. No.00TH8509).

[6]  A. Dupret,et al.  Image processing vision system implementing a smart sensor , 2004, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510).

[7]  Didier Demigny,et al.  Efficient ASIC and FPGA implementations of IIR filters for real time edge detection , 1997, Proceedings of International Conference on Image Processing.

[8]  Jaehyuk Choi,et al.  A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur , 2007, IEEE Journal of Solid-State Circuits.

[9]  David G. Lowe,et al.  Distinctive Image Features from Scale-Invariant Keypoints , 2004, International Journal of Computer Vision.

[10]  L. D. McIlrath.  A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm , 1996 .

[11]  Ralph Etienne-Cummings,et al.  Implementation of steerable spatiotemporal image filters on the focal plane , 2002 .

[12]  Tadashi Shibata,et al.  An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems , 2003, IEEE Trans. Neural Networks.

[13]  Ángel Rodríguez-Vázquez,et al.  A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage , 1997, IEEE J. Solid State Circuits.

[14]  Ralph Etienne-Cummings,et al.  A Vision Chip for Color Segmentation and Pattern Matching , 2003, EURASIP J. Adv. Signal Process..

[15]  Eric R. Fossum,et al.  CMOS image sensors: electronic camera-on-a-chip , 1997 .

[16]  Rachid Deriche.  Fast Algorithms for Low-Level Vision , 1990, IEEE Trans. Pattern Anal. Mach. Intell..

[17]  Tadashi Shibata,et al.  A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Zhimin Zhou,et al.  Frame-transfer CMOS active pixel sensor with pixel binning , 1997 .

[19]  Shoji Muramatsu,et al.  Image processing device for automotive vision systems , 2002, Intelligent Vehicle Symposium, 2002. IEEE.

[20]  Ralph Etienne-Cummings,et al.  A programmable focal-plane MIMD image processor chip , 2001 .

[21]  A. Olyaei,et al.  Focal-Plane Spatially Oversampling CMOS Image Compression Sensor , 2007, IEEE Trans. Circuits Syst. I Regul. Pap..

[22]  Junwei Guan,et al.  A 256×256–pixel smart CMOS image sensor for line based stereo vision applications , 1999 .

[23]  Piotr Dudek,et al.  A general-purpose processor-per-pixel analog SIMD vision chip , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Charles G. Sodini,et al.  A CCD/CMOS-Based Imager with Integrated Focal Plane Signal Processing (Special Section on the 1992 VLSI Circuits Symposium) , 1993 .

[25]  D. Seguine.  Just add sensor - integrating analog and digital signal conditioning in a programmable system on chip , 2002, Proceedings of IEEE Sensors.

[26]  Xinqiao Liu,et al.  A 10000 frames/s CMOS digital pixel sensor , 2001, IEEE J. Solid State Circuits.

[27]  S. Espejo,et al.  A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O , 2004, IEEE Journal of Solid-State Circuits.

[28]  Piotr Dudek,et al.  A CMOS general-purpose sampled-data analogue microprocessor , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[29]  D. Hubel,et al.  Receptive fields of single neurones in the cat's striate cortex , 1959, The Journal of physiology.

[30]  P. Hasler,et al.  A CMOS floating-gate matrix transform imager , 2005, IEEE Sensors Journal.

[31]  Larry H. Matthies,et al.  Multiresolution image sensor , 1997, IEEE Trans. Circuits Syst. Video Technol..

[32]  A. Dupret,et al.  On chip vision system architecture using a CMOS retina , 2004, IEEE Intelligent Vehicles Symposium, 2004.