Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology

In this paper, a new ten transistors (10T) SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell has six main body transistors similar to 6T bit-cell to perform write operation along with separate bitline discharging path (2T) on each side to perform read operation. Efficacy of the proposed bit-cell is tested in 20nm tri-gated FinFET technology with the help of HSPICE simulations at different supply voltages (0.6V to 0.9V). Performance characteristics of the proposed bit-cell are compared with the recently reported 10T P-P-N bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 12% and 41% higher RSNM as compared to that of 10T P-P-N and 6T bit-cells respectively at VDD of 0.6V. WM of proposed bit-cell is 34.88% higher and comparable to that of 10T P-P-N and 6T bit-cell respectively at VDD of 0.6V. Influence of process variation on proposed bit-cell stability is studied using 5,000 Monte Carlo simulations. The study shows that proposed bit-cell meets the required cell sigma value (6σ) for all operations at VDD of 0.6 V.

[1]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[2]  David Blaauw,et al.  Circuit and microarchitectural techniques for reducing cache leakage power , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  K. Banerjee,et al.  Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design , 2010, IEEE Transactions on Electron Devices.

[4]  Jinn-Shyan Wang,et al.  Sub-threshold SRAM bit cell pnn for VDDmin and power reduction , 2014 .

[5]  Benton H. Calhoun,et al.  Flexible Circuits and Architectures for Ultralow Power , 2010, Proceedings of the IEEE.

[6]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Behzad Ebrahimi,et al.  A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies , 2015, Integr..

[8]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[9]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[10]  S. Shimada,et al.  Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[11]  Ali M. Niknejad,et al.  Design of FinFET SRAM Cells Using a Statistical Compact Model , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[12]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[13]  Olivier Thomas,et al.  Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[14]  Behzad Ebrahimi,et al.  A high speed subthreshold SRAM cell design , 2009, 2009 1st Asia Symposium on Quality Electronic Design.

[15]  N. Planes,et al.  A New Combined Methodology for Write-Margin Extraction of Advanced SRAM , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

[16]  Carl Radens,et al.  A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements , 2011, IEEE Journal of Solid-State Circuits.

[17]  Tsutomu Yoshimura,et al.  Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Cristina Meinhardt,et al.  Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations , 2014, Microelectron. Reliab..

[19]  Kazuhiko Endo,et al.  Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation , 2010, IEEE Transactions on Electron Devices.

[20]  Jon Cartwright.  Intel enters the third dimension , 2011 .