Response-time properties of linear asynchronous pipelines

One of the potential advantages of asynchronous circuits is that they can be optimized for average-case performance rather than worst-case performance. The performance analysis of asynchronous circuits, however, is more challenging than that of synchronous circuits because of the absence of a clock. We discuss some performance measures of special asynchronous networks, viz., response-time properties of asynchronous pipelines with various handshake communications. The response times of a pipeline are the delays between requests and succeeding acknowledgments for the first cell. We derive simple formulas for the bound on worst-case response time and average-case response time of such pipelines using a variable-delay model, where delays may vary between a lower and upper bound. The properties are independent of any particular implementation of the cells of the pipeline. The formulas give insight into the role of each parameter and allow a quick back-of-the-envelope prediction of the performance of an asynchronous pipeline.

[1]  Steven Burns Performance Analysis and Optimization of Asynchronous Circuits , 1991 .

[2]  Martin Rem,et al.  Trace Theory and Systolic Computations , 1987, PARLE.

[3]  J. Sparso,et al.  Design and performance analysis of delay insensitive multi-ring structures , 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

[4]  Ad M. G. Peeters,et al.  Design and analysis of delay-insensitive modulo-N counters , 1993, Formal Methods Syst. Des..

[5]  Steven M. Burns,et al.  Bounded delay timing analysis of a class of CSP programs with choice , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[6]  Mark B. Josephs,et al.  Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[7]  Jo C. Ebergen,et al.  A Derivation of a Serial-Parallel Multiplier , 1990, Sci. Comput. Program..

[8]  Peter A. Beerel,et al.  Symbolic techniques for performance analysis of timed systems based on average time separation of events , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[9]  Gaetano Borriello,et al.  An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems , 1995, IEEE Trans. Computers.

[10]  Steve Furber Computing without Clocks: Micropipelining the ARM Processor , 1995 .

[11]  T. E. Williams Analyzing and improving the latency and throughput performance of self-timed pipelines and rings , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[12]  Martin Rem,et al.  VLSI Programming of Asynchronous Circuits for Low Power , 1995 .

[13]  Kees van Berkel VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power , 1993, Asynchronous Design Methodologies.

[14]  Neil W. Bergmann,et al.  Performance evaluation of asynchronous logic pipelines with data dependent processing delays , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[15]  Kenneth Steiglitz,et al.  Bubbles can make self-timed pipelines fast , 1990, J. VLSI Signal Process..

[16]  Michael Kishinevsky,et al.  Performance Analysis Based on Timing Simulation , 1994, 31st Design Automation Conference.

[17]  Igor Benko,et al.  Parallel Program and Asynchronous Circuit Design , 1995 .