An effective diagnosis method to support yield improvement

The ability to achieve and maintain high yield levels depends on the capability of detecting, analyzing and correcting repetitive failure mechanisms. In this paper, a statistical fault diagnosis method based on using only the first or the first few failing test vectors is presented. The new approach is analyzing the failing vectors from an entire lot and produces a finite list of suspect locations, which are then subjected to further statistical and physical analysis. The results of the performed case studies show the usefulness of this method when applied in a production environment. We were able to detect repetitive failure mechanisms and accurately correlate electrical fail locations to in-line inspection data and thus greatly improve the accuracy of the determined kill ratio.

[1]  Anjali Kinra,et al.  Logic mapping on a microprocessor , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[2]  Camelia Hora,et al.  On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up , 2003, J. Electron. Test..

[3]  Robert C. Aitken.  Modeling the Unmodelable: Algorithmic Fault Diagnosis , 1997, IEEE Des. Test Comput..

[4]  G. Sery,et al.  Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[5]  Young-Jun Kwon,et al.  Yield learning via functional test data , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[6]  Arun Gunda,et al.  Failure analysis for full-scan circuits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[7]  M.A. Merino,et al.  SmartBit/sup TM/: bitmap to defect correlation software for yield improvement , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[8]  D. M. H. Walker,et al.  Improvement of SRAM-based failure analysis using calibrated Iddq testing , 1996, Proceedings of 14th VLSI Test Symposium.

[9]  John M. Acken,et al.  Fault Model Evolution For Diagnosis: Accuracy vs Precision , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[10]  M. Lousberg,et al.  On Electrical Fault Diagnosis in Full-Scan Circuits , 2001 .

[11]  Kenneth M. Butler,et al.  Correlation of logical failures to a suspect process step , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  Wojciech Maly,et al.  Yield-oriented computer-aided defect diagnosis , 1995 .

[13]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[14]  W. Kent Fuchs,et al.  TWO-STAGE FAULT LOCATION , 1991, 1991, Proceedings. International Test Conference.