Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution (<1.5% sigma). First, a two-loop write–verify protocol is proposed. Then, statistical experiments are conducted on RRAM array fabricated in Winbond’s 90-nm process. By incorporating the measured conductance distribution into DNN simulation considering the real weight mapping, inference accuracy with only 0.5% degradation over software baseline is achieved for CIFAR-10 data set even when 128 rows are read-out in parallel. By enabling parallel read-out, the system-level energy efficiency and throughput could be improved by <inline-formula> <tex-math notation="LaTeX">$5.3 \times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.4 \times $ </tex-math></inline-formula>, respectively, compared to the 3-bit per cell RRAM used as MLC storage.

[1]  S. Ambrogio,et al.  Confined PCM-based Analog Synaptic Devices offering Low Resistance-drift and 1000 Programmable States for Deep Learning , 2019, 2019 Symposium on VLSI Technology.

[2]  Qing Wu,et al.  Efficient and self-adaptive in-situ learning in multilayer memristor neural networks , 2018, Nature Communications.

[3]  ChiaHua Ho,et al.  Integrated HfO2-RRAM to achieve highly reliable, greener, faster, cost-effective, and scaled devices , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[4]  Hyunsang Hwang,et al.  Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering , 2015, IEEE Electron Device Letters.

[5]  Bin Gao,et al.  Fully hardware-implemented memristor convolutional neural network , 2020, Nature.

[6]  A. Sebastian,et al.  8-bit Precision In-Memory Multiplication with Projected Phase-Change Memory , 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

[7]  Hyunsang Hwang,et al.  Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems , 2018, IEEE Electron Device Letters.

[8]  Xiaoyu Sun,et al.  Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks , 2019, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[9]  Shimeng Yu,et al.  A Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing , 2018, 2018 IEEE Symposium on VLSI Technology.

[10]  Xiaochen Peng,et al.  DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[11]  Xiaochen Peng,et al.  Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[12]  Jiaming Zhang,et al.  Analogue signal and image processing with large memristor crossbars , 2017, Nature Electronics.

[13]  Ligang Gao,et al.  Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories , 2015, IEEE Electron Device Letters.

[14]  John Paul Strachan,et al.  Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors , 2019, Advanced Electronic Materials.

[15]  P. Bousoulas,et al.  Low-Power and Highly Uniform 3-b Multilevel Switching in Forming Free TiO2–x-Based RRAM With Embedded Pt Nanocrystals , 2016, IEEE Electron Device Letters.

[16]  H.-S. Philip Wong,et al.  Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell , 2019, IEEE Transactions on Electron Devices.

[17]  Yandong Luo,et al.  Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine , 2020, IEEE Transactions on Electron Devices.

[18]  Zhengya Zhang,et al.  A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations , 2019, Nature Electronics.

[19]  P. Pavan,et al.  A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO2 RRAM , 2015, IEEE Electron Device Letters.

[20]  Shimeng Yu,et al.  Neuro-Inspired Computing With Emerging Nonvolatile Memorys , 2018, Proceedings of the IEEE.

[21]  D. J. Wouters,et al.  3-bit Resistive RAM Write-Read Scheme Based on Complementary Switching Mechanism , 2017, IEEE Electron Device Letters.

[22]  Fabien Alibart,et al.  Pattern classification by memristive crossbar circuits using ex situ and in situ training , 2013, Nature Communications.

[23]  Yandong Luo,et al.  Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction , 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

[24]  Ligang Gao,et al.  High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm , 2011, Nanotechnology.