New insight into the TDDB and breakdown reliability of novel high-к gate dielectric stacks

In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO2) have been replaced by physically thicker high-к transition metal oxide thin films by many manufacturers starting from the 45nm technology node. CMOS process compatibility, integration and reliability are the key issues to address while introducing high-к at the front end. In this study, we analyze in-depth the reliability aspect of high-к dielectrics focusing on both the time-dependent-dielectric breakdown (TDDB) and the post breakdown evolution stage. Electrical characterization, physical failure analysis, statistical reliability modeling as well as atomistic simulations have all been used to achieve a comprehensive understanding of the physics of failure in HK and the associated microstructural defects and failure mechanisms. The role played by different gate materials ranging from poly-Si → FUSI → metal gate and different HK materials (HfO2, HfSiON, HfZrO4) is also investigated. Based on the results obtained, we emphasize the need and propose a few approaches of design for reliability (DFR) in high-к gate stacks.

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