Constrained worst case loads for microprocessors

The risk of a microprocessor execution error increases as the voltage at the die decreases, making worst case analysis of the die voltage a good metric for microprocessor voltage regulation performance. However, the actual worst case load is unlikely to ever occur. This paper derives the results for the worst case load from linear system theory, and then uses a constrained optimization problem to calculate the worst case load under more probable circumstances, demonstrating that loads with much higher likelihood of occurrence can cause voltages at the die nearly as low as the worst case.

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