Low-power, high-linearity transconductor with a high tolerance for process and temperature variations

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post-layout are commensurate with pre-layout. Post-layout simulation results show that when temperature changes from − 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from  − 78 to −72dB at 1 MHz for 0.2 VPP input signal, −3 dB bandwidth changes from 2.5 to 5 GHz, input-referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW.

[1]  Ramón González Carvajal,et al.  Low-power CMOS variable gain amplifier based on a novel tunable transconductor , 2015, IET Circuits Devices Syst..

[2]  Fujihiko Matsumoto,et al.  Design of a linear transconductor considering effects of weak inversion region and mobility degradation , 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

[3]  Shunli Ma,et al.  A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  Maryam Shojaei Baghini,et al.  A Fully On-Chip PT-Invariant Transconductor , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Khanittha Kaewdang,et al.  A novel widely linear current-tunable CMOS transconductor , 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

[6]  Radu Gabriel Bozomitu,et al.  A Tunable Transconductor with Temperature and Process Immunity , 2018, 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging​ (SIITME).

[7]  Santiago Celma,et al.  Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  J. M. Algueta-Miguel,et al.  CMOS transconductor with improved linearity using the bulk of self-cascode transistors , 2017 .

[9]  Ramon Gonzalez Carvajal,et al.  A Tunable Pseudo-Differential OTA With $-78~{\hbox {dB}}$ THD Consuming 1.25 mW , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Nobuo Fujii,et al.  Highly-linear transconductor cell realised by double MOS transistor differential pairs , 1990 .

[11]  Chenming Hu,et al.  MOSFET Modeling & BSIM3 User’s Guide , 1999 .

[12]  Clara Isabel Lujan-Martinez,et al.  A compact voltage-controlled transconductor with high linearity , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[13]  Mohamad Sawan,et al.  A current tuneable fully differential transconductor dedicated for filtering applications , 2000, ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388).

[14]  Yichuang Sun,et al.  A Gm-C complex IF filter using fully differential transconductor for dual-mode GNSS receiver , 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

[15]  Soliman A. Mahmoud,et al.  A linear CMOS balanced output transconductor using double differential pair with source degeneration and adaptive biasing , 2016, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS).

[16]  Nagendra Krishnapura,et al.  Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[17]  W. Guggenbuhl,et al.  A voltage-controllable linear MOS transconductor using bias offset technique , 1990 .

[18]  Brent Maundy,et al.  A low voltage linearly tuned fully differential CMOS OTA and its applications in filter design , 2002, IEEE CCECE2002. Canadian Conference on Electrical and Computer Engineering. Conference Proceedings (Cat. No.02CH37373).

[19]  Sergio Bampi,et al.  CMOS transconductor analysis for low temperature sensitivity based on ZTC MOSFET condition , 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

[20]  Sang-Gug Lee,et al.  An IF Bandpass Filter Based on a Low Distortion Transconductor , 2010, IEEE Journal of Solid-State Circuits.

[21]  Fujihiko Matsumoto,et al.  Improvement technique of tuning range for local-feedback MOS transconductor , 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

[22]  Y. Noguchi,et al.  Technique to improve linearity of transconductor with bias offset voltages controlling a tail current , 2005 .

[23]  Ramón González Carvajal,et al.  A 1.2-V 450-μW $G_{m}$ - $C$ Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Ashok Nedungadi,et al.  Design of linear CMOS transconductance elements , 1984 .

[25]  Melanie Hartmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[26]  Clara Isabel Lujan-Martinez,et al.  A CMOS linear tunable transconductor for continuous-time tunable Gm-C filters , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[27]  J. Jakusz,et al.  Differential pair transconductor linearisation via electronically controlled current-mode cells , 1992 .

[28]  Chutham Sawigun,et al.  A low-voltage CMOS linear transconductor suitable for analog multiplier application , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[29]  Ramon Gonzalez Carvajal,et al.  A Tunable Pseudo-Differential OTA With � dB THD Consuming 1 . 25 mW , 2009 .

[30]  Ramón González Carvajal,et al.  Improved technique for continuous tuning of CMOS transconductor , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[31]  W. Kiranon,et al.  A linearized source-couple pair transconductor using a low-voltage square root circuit , 2008, 2008 5th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology.

[32]  José Silva-Martínez,et al.  A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[33]  Andrea Baschirotto,et al.  A 3 V pseudo-differential transconductor with intrinsic rejection of the common-mode input signal , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[34]  Sangwook Nam,et al.  A Transconductor and Tunable $G_{m}-C$ High-Pass Filter Linearization Technique Using Feedforward $G_{m3}$ Canceling , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.