Improving SRAM read/write margin with asymmetric halo MOSFET

We propose SRAM bitcells with asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks for halo implant steps. AH-MOS has different drain-source currents (Ids) between forward and reverse directions (Fig. 1). By implanting high and low dose for drain and source regions respectively, Ids flowing from drain to source (forward) gets larger than that from source to drain (reverse). Fig. 2 shows 6T SRAM bitcell with AH-MOS [1]. The current at pass-gate (PG), which consists of AH-MOS, flows bi-directionally in read and write mode. The pull-down (PD) is symmetric halo implant dose MOSFET (SH-MOS) due to unidirectional currents. The pull-up (PU) is also SH-MOS.

[1]  Ching-Te Chuang,et al.  Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors , 2009, IEEE Electron Device Letters.

[2]  Hidehiro Fujiwara,et al.  A dynamic body-biased SRAM with asymmetric halo implant MOSFETs , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[3]  Koji Nii,et al.  A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).