A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs

Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.

[1]  L. Sterpone,et al.  A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[2]  Edward Petersen,et al.  Single Event Effects in Aerospace: Petersen/Single Event Effects in Aerospace , 2011 .

[3]  Jiri Gaisler.  A portable and fault-tolerant microprocessor based on the SPARC v8 architecture , 2002, Proceedings International Conference on Dependable Systems and Networks.

[4]  Austin Lesea,et al.  Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits , 2008 .

[5]  A. Lesea,et al.  The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs , 2005, IEEE Transactions on Device and Materials Reliability.

[6]  Franc Novak,et al.  Automated SEU fault emulation using partial FPGA reconfiguration , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[7]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[8]  Ronald D. Schrimpf,et al.  Radiation Effects And Soft Errors In Integrated Circuits And Electronic Devices , 2004 .

[9]  Gabriel L. Nazar,et al.  Fast single-FPGA fault injection platform , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[10]  Massimo Violante,et al.  Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[11]  Luca Sterpone,et al.  Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture , 2013, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013).

[12]  J.M. Mogollon,et al.  FTUNSHADES2: A novel platform for early evaluation of robustness against SEE , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.

[13]  Alfredo Benso,et al.  Fault Injection Techniques and Tools for Embedded Systems , 2003 .

[14]  Javier Del Ser,et al.  Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs , 2014, IEEE Transactions on Industrial Electronics.

[15]  Paolo Prinetto,et al.  An area-efficient 2-D convolution implementation on FPGA for space applications , 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

[16]  Edward Petersen,et al.  Single Event Effects in Aerospace , 2011 .

[17]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[18]  Mengu Cho,et al.  Evaluation of SRAM based FPGA performance by simulating SEU through fault injection , 2013, 2013 6th International Conference on Recent Advances in Space Technologies (RAST).

[19]  Jean Arlat,et al.  Fault Injection for Dependability Validation: A Methodology and Some Applications , 1990, IEEE Trans. Software Eng..