A dual–rail PLA with 2–input logic cells

This paper presents a new dual-rail PLA with 2-input logic cells. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA without degradation of circuit performance. By using the logic cells, some classes of logic function can be implemented in a smaller circuit area, so that a high-speed and low-power operation is also achieved. The area advantage over the conventional design has been demonstrated by using PLA benchmark circuits. The measured results show that the proposed PLA operates correctly.

[1]  Kevin J. Nowka,et al.  Design methodology for a 1.0 GHz microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[2]  Kevin J. Nowka,et al.  "Timing closure by design," a high frequency microprocessor design methodology , 2000, Proceedings 37th Design Automation Conference.

[3]  K. Asada,et al.  A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[4]  Tsutomu Sasao,et al.  Input Variable Assignment and Output Phase Optimization of PLA's , 1984, IEEE Transactions on Computers.

[5]  Makoto Ikeda,et al.  Logic synthesis for PLA with 2-input logic elements , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  Makoto Ikeda,et al.  Logic synthesis for AND-XOR-OR type sense-amplifying PLA , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[7]  Robert K. Brayton,et al.  Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Martin S. Schmookler Design of large ALUs using multiple PLA macros , 1980 .

[9]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .