A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot be applied. To reduce the propagation delays of the S-Box, the slowest function block, we developed a special circuit architecture that we call twisted-binary decision diagram (BDD), where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.

[1]  Vincent Rijmen,et al.  The Design of Rijndael , 2002, Information Security and Cryptography.

[2]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.

[3]  Vijay Kumar,et al.  Efficient Rijndael Encryption Implementation with Composite Field Arithmetic , 2001, CHES.

[4]  Máire O'Neill,et al.  High Performance Single-Chip FPGA Rijndael Algorithm Implementations , 2001, CHES.

[5]  Ingrid Verbauwhede,et al.  Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm , 2001, CHES.

[6]  Christof Paar,et al.  Efficient Algorithms for Elliptic Curve Cryptosystems , 1997, CRYPTO.

[7]  Patrick Schaumont,et al.  Design and performance testing of a 2.29-GB/s Rijndael processor , 2003, IEEE J. Solid State Circuits.

[8]  Mitsuru Matsui,et al.  Hardware Evaluation of the AES Finalists , 2000, AES Candidate Conference.

[9]  Joan Daemen,et al.  AES Proposal : Rijndael , 1998 .

[10]  Toshiyuki Yamane,et al.  Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m) , 2001, CAV.

[11]  Wolfgang Rosenstiel,et al.  Efficient graph-based computation and manipulation of functional decision diagrams , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[12]  U. Mayer,et al.  Evaluation of different Rijndael implementations for high end servers , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[13]  Dirk Fox,et al.  Advanced Encryption Standard (AES) , 1999, Datenschutz und Datensicherheit.

[14]  Tsutomu Sasao.  And-Exor Expressions and their Optimization , 1993 .

[15]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[16]  Bryan Weeks,et al.  Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms , 2000, AES Candidate Conference.

[17]  Milos Drutarovský,et al.  Two Methods of Rijndael Implementation in Reconfigurable Hardware , 2001, CHES.