Multi-interval static timing analysis accounting logic compatibility

The influence of technological and circuit parameters variations on the combinational circuit elements delay increases with the transistor size reduction. Delay uncertainty comes from the parameter values dispersion; therefore, it is critical to analyze the possible delay variance. This paper presents the solution to problems of complex digital circuits performance analysis with the presence of the aforementioned uncertainty. In order to account technological and circuit element parameters uncertainty we propose a method which is based on interval modeling. Unlike the traditional analysis based on the test sequence modeling with ordering events during the time, the proposed method provides space ordering, thus it offers significant accuracy increase for interval delay analysis with simultaneous input switching consideration.