Design and demonstration of large 2.5D glass interposer for high bandwidth applications

In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm glass interposers with 300 um core thickness can be realized by utilizing semi additive process. Finally, 10mm × 10m dies with daisy chains can be successfully bonded to 25mm × 30mm glass interposer with 6 metal lines using copper microbumps with SnAg solder caps.

[1]  V. Sukumaran,et al.  Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[2]  E. J. Vardaman,et al.  Developments in 2.5D: The role of silicon interposers , 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).

[3]  Rao Tummala,et al.  Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[4]  Brett M. D. Sawyer,et al.  Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).