The Challenge of Hardware-Software Co-verification

Building verified computing systems such as a verified compiler or operating system will require both software and hardware verification. How can we decompose such verification efforts into mostly separate tasks, one involving hardware and the other software? What theorems should we prove? What specification languages should we use? What tools should we build? To what extent can the process be automated? We address these issues, using as a running example our recent and on-going work on refinement-based pipelined machine verification.

[1]  Panagiotis Manolios,et al.  Refinement maps for efficient verification of processor models , 2005, Design, Automation and Test in Europe.

[2]  Sanjit A. Seshia,et al.  Modeling and Verification of Out-of-Order Microprocessors in UCLID , 2002, FMCAD.

[3]  Kedar S. Namjoshi.  A Simple Characterization of Stuttering Bisimulation , 1997, FSTTCS.

[4]  Panagiotis Manolios,et al.  Verification of executable pipelined machines with bit-level interfaces , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  Panagiotis Manolios.  Correctness of Pipelined Machines , 2000, FMCAD.

[6]  Panagiotis Manolios,et al.  A complete compositional reasoning framework for the efficient verification of pipelined machines , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[7]  Sanjit A. Seshia,et al.  Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions , 2002, CAV.

[8]  Panagiotis Manolios.  Mechanical verification of reactive systems , 2001 .

[9]  J Strother Moore.  System verification , 2004, Journal of Automated Reasoning.

[10]  Panagiotis Manolios.  A Compositional Theory of Refinement for Branching Time , 2003, CHARME.

[11]  David L. Dill,et al.  Automatic verification of Pipelined Microprocessor Control , 1994, CAV.

[12]  Klaus Schneider.  Verification of Reactive Systems , 2004, Texts in Theoretical Computer Science.

[13]  Edmund M. Clarke,et al.  Characterizing Finite Kripke Structures in Propositional Temporal Logic , 1988, Theor. Comput. Sci..

[14]  Panagiotis Manolios,et al.  Automatic verification of safety and liveness for XScale-like processor models using WEB refinements , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[16]  Panagiotis Manolios,et al.  A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. , 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

[17]  Matthew Wilding,et al.  High-speed, analyzable simulators , 2000 .

[18]  C. A. R. Hoare,et al.  The verifying compiler: A grand challenge for computing research , 2003, JACM.

[19]  Robert S. Boyer,et al.  Integrating decision procedures into heuristic theorem provers: a case study of linear arithmetic , 1988 .

[20]  Manolios Sudarshan Srinivasan,et al.  A Suite of Hard ACL 2 Theorems Arising in Refinement-Based Processor Verification , 2004 .

[21]  Panagiotis Manolios,et al.  A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems , 2005, CHARME.

[22]  George J. Milne,et al.  Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.

[23]  David M. Russinoff,et al.  RTL verification: a floating-point multiplier , 2000 .

[24]  Randal E. Bryant,et al.  Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction , 2000, Proceedings 37th Design Automation Conference.