Novel Analog Calibration Technique for Current-Steering DACs

This paper presents a novel high-speed area-efficient analog calibration technique for current-steering (CS) digital-to-analog converters (DACs). Negative feedback is used to correct errors caused due to mismatch, process variation, temperature, or aging. A faster calibration cycle and smaller additional circuits are possible with analog calibration, compared to the more prevalent digital calibration techniques. The new calibration circuit is presented with the necessary theoretical details. To demonstrate this technique, a 10-bit binary-weighted CS DAC is implemented in a $$0.18\, \upmu \hbox {m}$$0.18μm CMOS process. With worst-case process parameter variations, simulated integral and differential nonlinearities of the calibrated DAC are less than $$\pm 0.32$$±0.32 LSB. The DAC occupies an area of approximately $$0.3\,\hbox {mm}^{2}$$0.3mm2.

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