Electrical performance modeling of unbalanced comb tree networks on advanced PCB interconnects for high-rate clock signal distribution

Usually, the routing process is made by non-specialists in electrical simulation that only meet the requirement of the standards. The aim of this work is to supply a new tool dedicated to assess the quality of the tree network routing. An innovative modeling method of advanced unbalanced interconnections called “comb tree” for distributing high speed clock signals is featured. The flow work summarizing the routine process of new design rule is established to enhance the performance of advanced packages for high speed circuits. The analytical approach for extracting the voltage transfer function corresponding to the electrical signal paths in function of tree branch parameters is fundamentally inspired from SIMO/SISO electrical circuit analogy. Doing so, the wideband characteristic impedances and propagation constants of elementary lines constituting the tree are extracted from geometrical and physical properties. A PCB prototype of unbalanced comb tree network over FR-4 substrate has been designed and manufactured for the experimental verification. Then, frequency analyses of different VTFs have been carried out. Less than 1dB of error has been found within the DC-3GHz bandwidth and less than 4 dB within 3-10GHz. In addition, time-domain analyses with 2 Gbps input signal has been realized. Excellent agreements between transient simulations and the proposed model have been established. The model developed is potentially useful for predicting the signal integrity and optimization process of unbalanced advanced PCB and on-chip tree interconnects.

[1]  X. Zeng,et al.  Design of GHz VLSI clock distribution circuit , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[2]  N Nakhla,et al.  A General Approach for Sensitivity Analysis of Distributed Interconnects in the Time Domain , 2011, IEEE Transactions on Microwave Theory and Techniques.

[3]  Sandip Kundu,et al.  On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs , 2012, J. Electron. Test..

[4]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[5]  Gregory A. Northrop,et al.  Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors , 1999, IBM Journal of Research and Development.

[6]  Parameswaran Ramanathan,et al.  Clock distribution in general VLSI circuits , 1994 .

[7]  D. Velenis,et al.  Effects of parameter variations and crosstalk on H-tree clock distribution networks , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[8]  Gang Qu,et al.  A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[9]  Ying-Khai Teh,et al.  A study and design of CMOS H-Tree clock distribution network in system-on-chip , 2009, 2009 IEEE 8th International Conference on ASIC.

[10]  J.F. Buckwalter,et al.  Predicting Microwave Digital Signal Integrity , 2009, IEEE Transactions on Advanced Packaging.

[11]  Dan Oh,et al.  Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems , 2010, IEEE Transactions on Advanced Packaging.

[12]  Marios C. Papaefthymiou,et al.  A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[13]  D. A. Frickey.  Conversions between S, Z, Y, H, ABCD, and T parameters which are valid for complex source and load impedances , 1994 .

[14]  Cheng-Kok Koh,et al.  UST/DME: a clock tree router for general skew constraints , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[15]  Joungho Kim,et al.  Special Issue on PCB Level Signal Integrity, Power Integrity, and EMC , 2010 .

[16]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Jun Fan,et al.  Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions , 2010, IEEE Transactions on Electromagnetic Compatibility.

[18]  Witold Pedrycz,et al.  Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Qing Zhu,et al.  High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  E. Bogatin.  Essential Principles of Signal Integrity , 2011, IEEE Microwave Magazine.

[21]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[22]  Eby G. Friedman,et al.  Clock Distribution Networks in 3-D Integrated Systems , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  B. Ravelo,et al.  Experimental Validations of a Simple PCB Interconnect Model for High-Rate Signal Integrity , 2012, IEEE Transactions on Electromagnetic Compatibility.

[24]  Ellis Horowitz,et al.  The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI , 1981, IEEE Transactions on Computers.

[25]  Blaise Ravelo,et al.  Cancellation of Delays in the High-Rate Interconnects with UWB NGD Active Cells , 2011 .

[26]  Yao-Wen Chang,et al.  Delay modeling for buffered RLY/RLC trees , 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

[27]  M. S. Maza,et al.  Analysis of clock distribution networks in the presence of crosstalk and groundbounce , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[28]  Blaise Ravelo,et al.  Analysis of multi-gigabits signal integrity through clock H-tree , 2013, Int. J. Circuit Theory Appl..

[29]  Seungyoung Ahn,et al.  Mixed-Mode ABCD Parameters: Theory and Application to Signal Integrity Analysis of PCB-Level Differential Interconnects , 2011, IEEE Transactions on Electromagnetic Compatibility.

[30]  Dr.K.Sri Rama Krishna,et al.  ANN Models for Microstrip Line Synthesis and Analysis , 2008 .

[31]  Ian Galton,et al.  Tree-Structured DEM DACs with Arbitrary Numbers of Levels , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[32]  Anestis Dounavis,et al.  RLC interconnect modeling using delay algebraic equations , 2009, 2009 IEEE Dallas Circuits and Systems Workshop (DCAS).

[33]  Chien-Nan Jimmy Liu,et al.  A Tree-Topology Multiplexer for Multiphase Clock System , 2009, IEEE Trans. Circuits Syst. I Regul. Pap..

[34]  Blaise Ravelo,et al.  TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS , 2011 .

[35]  Alina Deutsch,et al.  Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[36]  Eby G. Friedman,et al.  Clock distribution networks for 3-D ictegrated Circuits , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[37]  Blaise Ravelo,et al.  Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction , 2012 .

[38]  James L. Drewniak,et al.  Improved technique for extracting parameters of low-loss dielectrics on printed circuit boards , 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

[39]  C. Ferrandon,et al.  Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[40]  Eby G. Friedman,et al.  Repeater design to reduce delay and power in resistive interconnect , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[41]  Dimitrios Velenis,et al.  Effects of crosstalk noise on H-tree clock distribution networks , 2006, 2006 IEEE International Symposium on Circuits and Systems.