Poster: An Efficient Low Power & High Performance in MPSOC

Multiprocessor system-on-chip (MPSoC) architectures have risen as a prevalent answer to the ever-increasing performance & reduce the power consumption requirements, that are customized to a specific application have the potential to achieve very high performance, while additionally obliging low power consumption. The power consumed and performance of the system mainly depend on the memory and communication medium of processors. There are some issues involved in memory and communication of processors. In this paper we try to avoid those issues and show two separate techniques to increase performance and reduce the power consumption. The first technique is Scratch Pad Memory (SPM) Replacement rather than cache replacement, second technique is Network on Chip (NOC) rather than Advanced Microcontroller Bus Architecture (AMBA) communication medium between processors.

[1]  Wei Zhang,et al.  A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Nitin,et al.  A New Efficient Replacement Policy for Scratch Pad Memory , 2013, 2013 5th International Conference on Computational Intelligence and Communication Networks.

[3]  Sandi Habinc,et al.  AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[4]  Anantha Chandrakasan,et al.  SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect , 2014, IEEE Hot Chips Symposium.

[5]  Wei Zhang,et al.  A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[6]  Nitin,et al.  Replacement policies for scratch pad memory in embedded systems , 2011, TENCON 2011 - 2011 IEEE Region 10 Conference.

[7]  Francky Catthoor,et al.  Reuse analysis of indirectly indexed arrays , 2006, TODE.

[8]  Sourav Roy.  H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors , 2009, 2009 22nd International Conference on VLSI Design.

[9]  Bruce Mathewson.  The evolution of SOC interconnect and How NOC Fits Within It , 2010, Design Automation Conference.

[10]  Anantha Chandrakasan,et al.  SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).