论文信息 - Impact of CMOS scaling on single-event hard errors in space systems

Impact of CMOS scaling on single-event hard errors in space systems

Applications of highly scaled devices in space are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 /spl mu/m DRAMs. For feature sizes below 0.5 /spl mu/m, scaling theory predicts that low power devices will have much lower hard error rates than devices optimized for high speed.

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