Hardware/Software Organization of a High-Performance ATM Host Interface

A successful hardware/software architecture that resolves performance bottlenecks at the workstation-to-network host interface and offers high end-to-end performance is described. The solution reported carefully splits protocol processing functions into hardware and software implementations. The interface hardware is highly parallel and performs all per-cell functions with dedicated logic to maximize performance. Software provides support for the transfer of data between the interface and application memory, as well as the state management necessary for virtual circuit setup and maintenance. In addition, all higher-level protocol processing is implemented with host software. The prototype connects a RISC System/6000 to a SONET-based asynchronous transfer model (ATM) network carrying data at the OC-3c rate of 155 Mb/s. An experimental evaluation of the interface hardware and software has been performed. Several conclusions are drawn about this host interface architecture and the workstations to which it is connected. >

[1]  M. Zitterbart,et al.  High-speed transport components , 1991, IEEE Network.

[2]  G.S. Delp,et al.  Memory as a network abstraction , 1991, IEEE Network.

[3]  David D. Clark,et al.  Architectural considerations for a new generation of protocols , 1990, SIGCOMM '90.

[4]  Calton Pu,et al.  Quaject composition in the Synthesis kernel , 1991, Proceedings 1991 International Workshop on Object Orientation in Operating Systems.

[5]  W. David Sincoskie,et al.  Sunshine: A High-Performance Self-Routing Broadband Packet Switch Architecture , 1991, IEEE J. Sel. Areas Commun..

[6]  W. David Sincoskie,et al.  An overview of the AURORA gigabit testbed , 1992, [Proceedings] IEEE INFOCOM '92: The Conference on Computer Communications.

[7]  Calton Pu,et al.  The Synthesis Kernel , 1988, Comput. Syst..

[8]  HE Ixtroductiont,et al.  The Bell System Technical Journal , 2022 .

[9]  Andy Hopper,et al.  The Cambridge Backbone Ring , 1990, Proceedings. IEEE INFOCOM '90: Ninth Annual Joint Conference of the IEEE Computer and Communications Societies@m_The Multiple Facets of Integration.

[10]  Jonathan M. Smith,et al.  A High-Performance Host Interface for ATM Networks , 1991, SIGCOMM.

[11]  K Thompson,et al.  UNIX implementation , 1986 .

[12]  Yechiam Yemini,et al.  Psi: A Silicon Compiler for Very Fast Protocol Processing , 1989 .

[13]  J. Lumley,et al.  A high-throughput network interface to a RISC workstation , 1992, IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems.

[14]  Jonathan M. Smith,et al.  A high-performance host interface for ATM networks , 1991, SIGCOMM 1991.

[15]  H. T. Kung,et al.  The design of nectar: a network backplane for heterogeneous multicomputers , 1989, ASPLOS III.

[16]  T. J. Robe,et al.  A SONET STS-3c user network interface IC , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[17]  Computer Staff.  Gigabit network testbeds , 1990, Computer.

[18]  Matra Harris,et al.  Protocol and interface for ATM LANs , 1992 .

[19]  W. David Sincoskie,et al.  The AURORA Gigabit Testbed , 1993, Comput. Networks ISDN Syst..

[20]  F. Bitz,et al.  Host interface design for ATM LANs , 1991, [1991] Proceedings 16th Conference on Local Computer Networks.

[21]  Israel Cidon,et al.  Paris: An approach to integrated high‐speed private networks , 1988 .

[22]  Brian Zill,et al.  Protocol implementation on the Nectar Communication Processor , 1990, SIGCOMM '90.

[23]  David R. Cheriton,et al.  The VMP network adapter board (NAB): high-performance network communication for multiprocessors , 1988, SIGCOMM '88.

[24]  Bruce S. Davie.  A host-network interface architecture for ATM , 1991, SIGCOMM '91.

[25]  Bruce S. Davie,et al.  Host interface design for experimental, very high-speed networks , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[26]  H. T. Kung,et al.  The design of nectar: a network backplane for heterogeneous multicomputers , 1989, ASPLOS 1989.

[27]  H. B. Bakoglu,et al.  The IBM RISC System/6000 Processor: Hardware Overview , 1990, IBM J. Res. Dev..

[28]  K. Thompson,et al.  UNIX time-sharing system: UNIX implementation , 1978, The Bell System Technical Journal.

[29]  Jeffrey C. Mogul,et al.  The effect of context switches on cache performance , 1991, ASPLOS IV.