A Novel Interconnection Approach for Globally Asynchronous Locally Synchronous Circuits

This paper introduces a new methodology to solve the interfacing problem in Globally Asynchronous Locally Synchronous (GALS) design approaches. We present a generic high-speed and delay-insensitive connector based on asynchronous four state logic (FSL). The advantages of this approach are following: First, it provides flexibility in the time domain since the data transfer is based on local handshakes and does not depend anymore on a global clock signal. Consequently, it removes timing constraints and even enables local optimizations. Second, this approach only requires a small number of interfacing signals, thus reducing the routing resources needed between data source and sink. Furthermore, the proposed architecture does not require customized delay lines and thus suits well for both ASIC and FPGA platforms. A modified FlexRay bus analyzer tool has been used to illustrate the advantages of our approach: High-speed and delayinsensitive data communication between different clock domains.