Serial and Parallel TAM Designs for System-on-Chip Interconnects Based on 2-Pattern Testability

Testing crosstalk-induced faults on interconnects of system-on-chip (SoC) has become more important because of high integration of semiconductors. The faults can be tested by 2pattern testing. 2-pattern testing means application of consecutive two test patterns and observation of one test response. In this paper, we present two DFT methods for 2-pattern testability of interconnect. One DFT method utilizes EXTEST mode of IEEE P1500 wrappers and achieves 2-pattern test through a serial TAM. The other method doesn’t use IEEE P1500 wrappers, but utilizes existing interconnects as much as possible in order to achieve 2-pattern test. In case studies, we show advantages that hardware overhead of the proposed method is lower than that of our previous DFT method based on consecutive testability.