Logic Synthesis for a Regular Layout
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Yang Xu | Marek A. Perkowski | Malgorzata Chrzanowska-Jeske | Yang Xu | M. Perkowski | M. Chrzanowska-Jeske
[1] S. L. Hurst,et al. A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods , 1978, IEEE Transactions on Computers.
[2] Yang Xu,et al. Optimized embedding of an incomplete binary tree in a two-dimensional array of programmable logic blocks , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.
[3] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[4] Malgorzata Chrzanowska-Jeske,et al. A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays , 1994, 31st Design Automation Conference.
[5] Fabio Somenzi,et al. Symmetry detection and dynamic variable ordering of decision diagrams , 1994, ICCAD '94.
[6] Malgorzata Marek-Sadowska,et al. Generalized Reed-Muller Forms as a Tool to Detect Symmetries , 1996, IEEE Trans. Computers.
[7] M. Chrzanowska-Jeske,et al. A regular representation for mapping to fine-grain, locally-connected FPGAs , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[8] Michael A. Harrison,et al. Algebraic Properties of Symmetric and Partially Symmetric Boolean Functions , 1963, IEEE Trans. Electron. Comput..
[9] 김보관,et al. Logic Synthesis and Optimization , 1991 .
[10] Sheldon B. Akers. A Rectangular Logic Array , 1972, IEEE Trans. Computers.
[11] Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.