A novel approach for reversible realization of 8-bit adder-subtractor circuit with optimized quantum cost

Low power efficient digital devices are target of researchers in recent years. This aim attracted researchers to focus on the reversible digital circuit design approach. In ideal situations reversible circuits generate zero power loss with improved performance. Reversible circuit design approach is increasingly applied in the area of DNA computing, low power CMOS design, nanotechnology, quantum computing and optical computing etc. This paper presents two design approaches for reversible realization of 8-bit adder-subtractor circuit with optimized quantum cost. These designs are compared with existing designs on some selected performance parameters such as total number of reversible gates, garbage outputs and quantum cost. The proposed design for 8-bit adder-subtractor circuit using reversible approach simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This optimized circuit may be utilized further for the designing of low power computing devices.

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