Design for strong testability of RTL data paths to provide complete fault efficiency

In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation time than the full scan method, and also improves test application time drastically compared with the full scan method.

[1]  Niraj K. Jha,et al.  A design for testability technique for RTL circuits using control/data flow extraction , 1996, ICCAD 1996.

[2]  Niraj K. Jha,et al.  Design for hierarchical testability of RTL circuits obtained by behavioral synthesis , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[3]  Niraj K. Jha,et al.  Design for hierarchical testability of RTL circuits obtained by behavioral synthesis , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Edward J. McCluskey,et al.  High-level synthesis for orthogonal scan , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[5]  Sujit Dey,et al.  H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads , 1996, Proceedings of 14th VLSI Test Symposium.

[6]  John P. Hayes,et al.  Hierarchical test generation using precomputed tests for modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Peter Duzy,et al.  The Synthesis Approach to Digital System Design , 1992 .

[8]  Edward J. McCluskey,et al.  Orthogonal scan: low overhead scan for data paths , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[9]  Niraj K. Jha,et al.  Genesis: a behavioral synthesis system for hierarchical testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.