Design and Analysis of Testable Mutual Exclusion Elements
暂无分享,去创建一个
Melvin A. Breuer | Peter A. Beerel | Matheus T. Moreira | Ney Laert Vilar Calazans | Yang Zhang | Leandro S. Heck | David Zar
[1] Peter A. Beerel,et al. A Designer's Guide to Asynchronous VLSI , 2010 .
[2] Andrew Lines,et al. Asynchronous interconnect for synchronous SoC design , 2004, IEEE Micro.
[3] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[4] Fernando Gehm Moraes,et al. Hermes-AA: A 65nm asynchronous NoC router with adaptive routing , 2010, 23rd IEEE International SOC Conference.
[5] D. J. Kinniment. Synchronization and Arbitration in Digital Systems , 2008 .
[6] Suwen Yang,et al. Synchronizer Performance in Deep Sub-Micron Technology , 2011, 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems.
[7] Matheus T. Moreira,et al. A 65nm standard cell set and flow dedicated to automated asynchronous circuits design , 2011, 2011 IEEE International SOC Conference.
[8] Ran Ginosar,et al. QNoC Asynchronous Router with Dynamic Virtual Channel Allocation , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[9] Rajit Manohar,et al. Non-uniform access asynchronous register files , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..
[10] Luciano Lavagno,et al. Asynchronous on-chip networks , 2005 .
[11] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[12] Suwen Yang,et al. Computing Synchronizer Failure Probabilities , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[13] Salomon Beer,et al. MTBF Bounds for Multistage Synchronizers , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.
[14] Se June Hong,et al. Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks , 1971, IEEE Transactions on Computers.
[15] Davide Bertozzi,et al. A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[16] Ad M. G. Peeters,et al. Stretching quasi delay insensitivity by means of extended isochronic forks , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.
[17] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[18] Mark R. Greenstreet,et al. Verifying an Arbiter Circuit , 2008, 2008 Formal Methods in Computer-Aided Design.
[19] Suwen Yang,et al. Synchronizer Behavior and Analysis , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.