A High Performance Computing Architecture for Real-Time Digital Emulation of RF Interactions

A high performance architecture for emulating realtime radio frequency systems is presented. The architecture is developed based on a novel compute model and uses nearmemory techniques coupled with highly distributed autonomous control to simultaneously optimize throughput and minimize latency. A cycle level C++ based simulator is used to validate the proposed architecture with simulation of complex RF scenarios.

[1]  J. Romberg,et al.  A Configurable Architecture for Efficient Sparse FIR Computation in Real-time Radio Frequency Systems , 2022, 2022 IEEE/MTT-S International Microwave Symposium - IMS 2022.

[2]  Miead Tehrani Moayyed,et al.  Colosseum: Large-Scale Wireless Experimentation Through Hardware-in-the-Loop Network Emulation , 2021, 2021 IEEE International Symposium on Dynamic Spectrum Access Networks (DySPAN).

[3]  Madhavan Swaminathan,et al.  Anisotropic Scatterer Models for Representing RCS of Complex Objects , 2021, 2021 IEEE Radar Conference (RadarConf21).

[4]  Pingfan Meng,et al.  Designing a hardware in the loop wireless digital channel emulator for software defined radio , 2012, 2012 International Conference on Field-Programmable Technology.

[5]  M. A. Wickert,et al.  Implementation of a real-time, frequency selective, RF channel simulator using a hybrid DSP-FPGA architecture , 2000, RAWCON 2000. 2000 IEEE Radio and Wireless Conference (Cat. No.00EX404).

[6]  Bok Young Kim,et al.  Petabit-Scale Silicon Photonic Interconnects With Integrated Kerr Frequency Combs , 2022, IEEE Journal of Selected Topics in Quantum Electronics.

[7]  Qixiang Cheng,et al.  Optical interconnection networks for high-performance systems , 2020, Optical Fiber Telecommunications VII.