Open-source circuit simulation tools for RF compact semiconductor device modelling

MOS-Modelle und Parameterextraktion Arbeitskreis MOS-AK is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high-level behavioural modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open-source compact model standardization activities and presents advanced topics in metal-oxide-semiconductor field-effect transistor modelling, focusing in particular on analogue/radio frequency applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The open-source computer-aided design tools Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated radio frequency model performance is evaluated and compared with experimental results for 90nm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.

[1]  Antonios Bazigos,et al.  High‐frequency scalable compact modelling of Si RF‐CMOS technology , 2008 .

[2]  Mike Brinson,et al.  Modelling of high-frequency inductance with Qucs non-linear radio frequency equation defined devices , 2009 .

[3]  Timothy A. Davis,et al.  Algorithm 907 , 2010 .

[4]  M. Bucher,et al.  EKV3 Parameter Extraction and Characterization of 90nm RF-CMOS Technology , 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

[5]  Angelos Antonopoulos,et al.  Bias Dependence of Low Frequency Noise in 90nm CMOS , 2010 .

[6]  Matthias Bucher,et al.  Why‐ and how‐ to integrate Verilog‐A compact models in SPICE simulators , 2013, Int. J. Circuit Theory Appl..

[7]  W. Grabinski,et al.  Compact modeling of low-power and RF analogue MOSFET devices , 2003 .

[8]  W. Curtice A MESFET Model for Use in the Design of GaAs Integrated Circuits , 1980 .

[9]  Matthias Bucher,et al.  Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model , 2003 .

[10]  L. Lemaitre,et al.  COMPACT DEVICE MODELING USING VERILOG-AMS AND ADMS , 2003 .

[11]  P. Nenzi,et al.  KLU sparse direct linear solver implementation into NGSPICE , 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

[12]  C. Enz,et al.  MOS transistor modeling for RF IC design , 2000, IEEE Journal of Solid-State Circuits.

[13]  Angelos Antonopoulos,et al.  Measurement and modelling of 1/f noise in 180 nm NMOS and PMOS devices , 2010, Proceedings of Papers 5th European Conference on Circuits and Systems for Communications (ECCSC'10).

[14]  Maria-Anna Chalkiadaki,et al.  Large-Signal RF Modeling with the EKV3 MOSFET Model , 2010 .

[15]  Antonios Bazigos,et al.  An efficient channel segmentation approach for a large-signal NQS MOSFET model , 2008 .

[16]  G.J. Coram,et al.  How to (and how not to) write a compact model in Verilog-A , 2004, Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004..

[17]  Mike Brinson,et al.  Interactive compact device modelling using Qucs equation-defined devices , 2008 .

[18]  Michael Schroter High-Frequency Circuit Design Oriented Compact Bipolar Transistor Modeling with HICUM , 2005 .

[19]  Mike Brinson,et al.  Qucs: A GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond , 2009 .

[20]  W. Grabinski,et al.  Standardization of the compact model coding: non-fully depleted SOI MOSFET example , 2005 .

[21]  L. Lemaitre,et al.  Extensions to Verilog-A to support compact device modeling , 2003, Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation.

[22]  L. Lemaitre,et al.  ADMS-automatic device model synthesizer , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[23]  Angelos Antonopoulos,et al.  CMOS RF noise, scaling, and compact modeling for RFIC design , 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).