论文信息 - Efficient test cost reduction procedure for parallel-serial scan circuits

Efficient test cost reduction procedure for parallel-serial scan circuits

An efficient test generation procedure aimed at reducing test application cost in parallel-serial scan (PASE-scan) circuits is presented. The procedure is based on the structure and configuration of this type of full-scan circuits. The results obtained with a set of ISCAS89 benchmark circuits are provided, showing the effectiveness of this technique as regards test clock reduction.

J. M. Solana

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