Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.

[1]  Sheng-Tsai Wu,et al.  Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) , 2011 .

[2]  P. Tzeng,et al.  Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[3]  Lars Brusberg,et al.  Glass panel processing for electrical and optical packaging , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[4]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[5]  H. Reichl,et al.  3D integration of image sensor SiP using TSV silicon interposer , 2009, 2009 11th Electronics Packaging Technology Conference.

[6]  John H. Lau,et al.  Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates , 2010 .

[7]  Kuo-Shu Kao,et al.  Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[8]  W. Landers,et al.  3D copper TSV integration, testing and reliability , 2011, 2011 International Electron Devices Meeting.

[9]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[10]  John H. Lau,et al.  Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps , 2009, 2009 59th Electronic Components and Technology Conference.

[11]  John H. Lau,et al.  An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration , 2011 .

[12]  D. Pinjala,et al.  Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages , 2009, IEEE Transactions on Components and Packaging Technologies.

[13]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[14]  Christian Baks,et al.  Terabit/sec-class board-level optical interconnects through polymer waveguides using 24-channel bidirectional transceiver modules , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[15]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[16]  V. Lee,et al.  Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[17]  H. Noma,et al.  IMC bonding for 3D interconnection , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[18]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[19]  K. Y. Au,et al.  3D chip stacking & reliability using TSV-micro C4 solder interconnection , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[20]  K. Saban.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[21]  M. Sunohara,et al.  Studies on electrical performance and thermal stress of a silicon interposer with TSVs , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[22]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[23]  Seung Wook Yoon,et al.  Development of Super Thin TSV PoP , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[24]  K. Zoschke,et al.  3D image sensor SiP with TSV silicon interposer , 2009, 2009 59th Electronic Components and Technology Conference.