Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Abstract A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. The four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.