Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems

In this paper, we present architecture, physical design, and implementation of Array Signal Processor (ASP) which performs phased array beamforming for sector imaging systems, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. The architecture is Cycle stealing DMA based delay and sum (DAS) with dynamic receive focus support. The processor supports 8 channels, operates up to 20 MHz sampling frequency and streams LVDS input data upto 280 Mbps (14 bit ADC). It supports up to 65 fps, 61 beams per frame to support a Field Of View (FOV) of 60 degrees with 1-degree lateral resolution. The dynamic receive focus supports a resolution of 64 samples per beam up to near field, and based on sampling frequency the resolution is achievable up to 1.2 mm. The physical design is targeted 180nm SCL™ technology, and we used CANENCE™ toolchain for physical design and Synopsis™ Prime Time (PT) for timing closure. The power consumption of the ASIC is 440mW and physical size is 5mm x 5mm. The package selected is 80 pin LQFN and accordingly, bonding diagram is designed.

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